In today's rapidly developing semiconductor manufacturing industry, there is a constant drive to increase levels of integration and reduce chip size by reducing device feature sizes. Because of other advances in semiconductor device processing capabilities, it would be desirable and advantageous to produce increasingly miniaturized physical structures such as transistor gates and the like, that have dimensions such as gate lengths, on the order of 10 nanometers.
Existing limitations in presently available photolithography processes make it difficult to produce the ultra narrow device features needed to keep up with other advancing aspects of semiconductor manufacturing technology. Some previous attempts at reducing device feature sizes include photoresist trimming and hardmask trimming. Photoresist trimming is difficult to do because of the photoresist thicknesses required for sub-193 nm or sub-157 nm photoresist. Hardmask trimming typically results in rough edges and uncertain critical dimensions of the device structure being produced.
It would therefore be desirable to produce semiconductor device features such as transistor gates, that have dimensions on the order of 10 nanometers.